library ieee;
use ieee.std_logic_1164.all;

entity uartModule is
	generic(DBIT: integer:=8;       -- # data bits
              SB_TICK: integer:=16;   -- # ticks for stop bits. 16/24/32 
              DVSR: integer:= 163;    -- baud rate divisor
              DVSR_BIT: integer:=8   -- # bits of DVSR
		  );
	port(
		--generales:
		clk, reset: in std_logic;
		--transferencia:
		rx: in std_logic;
		tx: out std_logic;
		--salidas:
		rx_done_tick: out std_logic;
		tx_done_tick: out std_logic;
		--entradas:
		tx_start: in std_logic;
		--datos
		dout: out std_logic_vector(DBIT-1 downto 0);
		din: in std_logic_vector(DBIT-1 downto 0)
	    );
end entity;

architecture arch of uartModule is
	signal tick: std_logic;
begin
baud_gen_unit: entity work.mod_m_counter(arch)
	generic map(M=>DVSR, N=>DVSR_BIT)
	port map(clk => clk, reset => reset,
			q=> open, max_tick=> tick);

UART0_RX:entity work.uart_rx(arch)
	generic map(DBIT=>DBIT, SB_TICK=>SB_TICK)
	port map(clk=>clk, reset=>reset, s_tick => tick,
		rx=> rx, rx_done_tick => rx_done_tick,
		dout=> dout);

UART0_TX:entity work.uart_tx(arch)
		generic map(DBIT=>DBIT, SB_TICK=>SB_TICK)
		port map(clk=>clk, reset=>reset,
			tx_start=>tx_start,
			s_tick=>tick, din=>din,
			tx_done_tick=>tx_done_tick, tx=>tx);
end arch;
